Electronic components are commonly tested over a plurality of channels, necessitating multiple banks of stimulus generation and response measurement. The testing equipment is typically constructed using more than one integrated circuit (IC) and many analog support components for each bank of channels to enable precision timing. Additionally, components such as multiple custom digital application-specific integrated circuits (ASICS), programmable delay lines and programmable clock generators are also required. The multiple ICs, analog components and various additional components, in particular the custom ASICs, require significant board space and expense. Also, alignment of timing between the banks is typically slow and difficult to maintain.
There is therefore a need to provide efficient precision timing of stimulus generation and response measurement over multiple banks with smaller design and less expense.